DocumentCode :
3576086
Title :
Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits
Author :
Jayashree, H.V. ; Agarwal, V.K. ; Charan, P. Venkatasree ; Kariappa, A. M. Chirag
Author_Institution :
Dept. of ECE, P.E.S. Inst. of Technol., Bangalore, India
fYear :
2014
Firstpage :
21
Lastpage :
24
Abstract :
Reversible logic is the emerging topic for research due to its advantage of low energy consumption. Fault tolerant circuit design is required to give error free outputs. In this paper we present an optimized n bit Reversible Fault Tolerant Comparator design using parity preserving reversible logic gates. The Design involves MSB comparison as the first stage followed by Next Bit comparison stage which contributes for 1 bit garbage-less comparator design. The Design is generalized for n bit comparison. The performance parameters are analyzed for n bit. Our work outperforms the existing reversible fault tolerant comparator designs in terms of garbage output and Ancilla inputs or constant inputs. This efficiency of our design helps in reducing the footprint of the design.
Keywords :
comparators (circuits); logic design; logic gates; low-power electronics; Ancilla bits; Ancilla inputs; bit reversible comparator; constant inputs; fault tolerant circuit design; fault tolerant design; garbage optimization; low energy consumption; next bit comparison stage; reversible fault tolerant comparator design; reversible logic gates; word length 1 bit; Equations; Fault tolerance; Fault tolerant systems; Logic gates; Mathematical model; Quantum computing; Very large scale integration; Comparator; Fault tolerant; Reversible; constant input; garbage output;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits, Communication, Control and Computing (I4C), 2014 International Conference on
Print_ISBN :
978-1-4799-6545-8
Type :
conf
DOI :
10.1109/CIMCA.2014.7057748
Filename :
7057748
Link To Document :
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