Board level JTAG/boundary scan test solution

The In-circuit-Tester (ICI) demands large volume of physical test points on PCB, which makes the PCB size bigger and also the cost of ICT test technology is very high, so there is a need for low cost PCB test technology, which allows the miniaturization of PCBs with simple design rules[1]. The solution is `Boundary Scan´. Implementation of IEEE1149.1boundary scan test standard into the ICs contributed drastically to the miniaturization of PCB assembly. This paper presents the applications of JTAG boundary scan test solution and the development of Boundary scan test solution using JTAG Provision for `Main Processor Unit´(MPU). MPU contains Altera´s one number EP3C40, two numbers EP3C2S FPGAs, four numbers Analog device´s ADSP-BFS48 and One Marvels 88E1111 PHY Boundary scan compatible ICs. From the experiments, it is observed that boundary scan test solution to MPU reduces the test time from several hours to 1 min 52 seconds compared to conventional testing.