Design and synthesis of dual key based AES encryption

Key aspect of communication is security. Encryption of information to make it inaccessible to unauthorized recipients is a main area in network security. AES encryption is one of the most secure encryption algorithms. But with improving technology, attacks which can be used for easy cryptanalysis of encrypted information have been developed. One of the main reasons for vulnerability of AES encryption algorithm is the use of static S-Boxes. Also with attempts made to tap the key, AES has become more vulnerable to cryptanalysis attacks. Static S-Boxes make it very easy for reverse engineering which form the basis of Super S-Box attack. Hence there have been a lot of proposals for generation of S-Boxes which are key dependent. Majority of those algorithms involve probabilistic methods which are very complicated for hardware implementation. In this paper, we present a synthesizable algorithm which involves the use of conventional bitwise operations for generation of key dependent S-Boxes. Also a dual key based AES is presented in the paper which is FPGA implementable. The algorithm is reliable in terms of security and also suitable for hardware implementation. Mathematical analyses have been carried out on the algorithm to compute the reliability.