Title :
Post synthesis optimization of reversible logic functions with extended template matching
Author :
Jayashree, H.V. ; Agrawal, V.K. ; Bharadwaj, N. Shishir
Author_Institution :
Dept. of ECE, P.E.S. Inst. of Technol., Bangalore, India
Abstract :
Research affinity towards Reversible Computing is increasing day to day due to its lower energy dissipation computing capability. To evaluate any reversible function it is necessary to build the system with reversible gates. In view of this there are many new reversible logic gates proposed by many authors. Quantum cost of few reversible gates are unpublished. Simplified version of transformation technique to synthesize new reversible gates with Fredkin and Toffoli gates network are presented in this paper. Post synthesis optimization with the new set of templates are carried out to reduce the Quantum cost.
Keywords :
circuit optimisation; logic design; logic gates; Fredkin gate network; Toffoli gate network; extended template matching; post synthesis optimization; reversible computing; reversible gate; reversible logic functions; reversible logic gates; Algorithm design and analysis; Arrays; Fault tolerance; Fault tolerant systems; Logic gates; Merging; Optimization; Fredkin; New Reversible gates; Toffoli; Transformation; synthesis;
Conference_Titel :
Circuits, Communication, Control and Computing (I4C), 2014 International Conference on
Print_ISBN :
978-1-4799-6545-8
DOI :
10.1109/CIMCA.2014.7057825
