Title :
Testability of circuits derived from lattice diagrams
Author :
Drechsler, Rolf ; Günther, Wolfgang ; Becker, Bernd
Author_Institution :
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
Abstract :
In this paper the testability of circuits derived from BDDs representing totally symmetric functions is analyzed. A test pattern generation technique is presented that has runtime linear in the size of the BDD. The result is directly applicable to circuits derived from lattice diagrams, a new design style that combines the synthesis and the layout step. Experimental results show that complete test generation for functions with more than 500 variables can be done in less than 1 CPU second
Keywords :
Boolean functions; binary decision diagrams; circuit testing; logic CAD; logic testing; BDD; binary decision diagrams; circuit testability; experimental results; lattice diagrams; test pattern generation technique; totally symmetric functions; Binary decision diagrams; Boolean functions; Circuit synthesis; Circuit testing; Computer science; Data structures; Field programmable gate arrays; Lattices; Logic circuits; Test pattern generators;
Conference_Titel :
Euromicro Conference, 2000. Proceedings of the 26th
Conference_Location :
Maastricht
Print_ISBN :
0-7695-0780-8
DOI :
10.1109/EURMIC.2000.874632
