Counter based superscalar instruction issuing

New techniques for superscalar instruction issuing are presented. It is shown that the data dependency check for both in-order and out-of-order issuing can be performed in O(log w) gate delay using O(w ²) primitive gates, where w is the size of the instruction buffer. Furthermore, we present a new counting-based technique for assigning instructions to resources. It requires a delay of O(log w + log m) and an area of O(w²log m + mw log k), where m is the number of instruction classes and k is the number of functional units. Finally, we investigate the consequences of executing the data dependency check in parallel with the resource conflict check