Achieving minimal and deterministic interrupt execution in stack-based processor architectures

Whilst stack-processors have enjoyed a renewed interest since the emergence of JAVA technology, stack-processors suffer from a major bottleneck-the constant movement of stack content to and from memory (stack-spilling). With 70% and 80% of instructions generating a stack-spill, performance can be significantly diminished in the absence of a cache. In order to overcome this problem, very small and simple `stack buffers´ may be used to eliminate virtually all stack-spills for very little cost in silicon. Unfortunately this introduces an indeterministic element of system behaviour, especially with respect to interrupts. In this paper the positive benefits of stack-buffers are assessed, as well as the penalties introduced in terms of interrupt performance in a stack-based architecture. Then a new mechanism for managing interrupt conditions with stack buffers, “stack buffer windowing” is presented. This is shown to deliver deterministic interrupt response whilst maintaining the reduced stack-spill overheads associated with normal buffering schemes