SystemC based hardware synthesis becomes reality

Summary form only given. The advances in ASIC technology have enabled the design of systems-on-chip (SoC). The complexity associated with SoC is creating many new challenges at all levels of the design process. The article discusses SystemC, an open community C++ modeling platform for system-level design and hardware/software co-design. SystemC is broadly supported by a large and growing number of leading system houses, semiconductor companies, intellectual property (IP) providers, embedded systems and EDA tool vendors through the Open SystemC Initiative (OSCI). The objective of the OSCI is to engender a whole new market for system-level design solutions, based on its support of SystemC and a common modeling platform with built-in interoperability. In order to gain acceptance from the SoC engineering community, the new standard modeling platform has to be more than just a means of communication; it has to support all kinds of features that can help to solve their most burning issue, namely “time-to-market”. For SoC, it is essential to support the reuse of intellectual property (IP) for multiple designs. That in turn means the support of IP creation as well as IP integration. Until recently, the synthesis tools required VHDL/Verilog descriptions as the design entry language, which of course was one good reason for hardware engineers not to adopt SystemC in their design flow. In June 2000, Synopsys introduced SystemC Compiler, a synthesis tool that allows one to synthesise hardware IP from a synthesizable subset of SystemC, thereby removing one of the biggest hurdles for the adoption of SystemC by the hardware design community