• DocumentCode
    3577828
  • Title

    Scalable Logic Gate Non-Volatile Memory

  • Author

    Lee Wang ; Shi-Ming Hsu

  • Author_Institution
    FlashSilicon Inc., Zhubei, Taiwan
  • fYear
    2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Scalable Logic Gate Non-Volatile Memory (SLGNVM) devices fabricated with standard CMOS logic process have been demonstrated with 110 nm, 55 nm, and 40 nm nodes. The cell sizes for the NOR flash array complied with the process design rules of the CMOS logic nodes are 0.5424 μm2, 0.2287 μm2, and 0.1095 μm2, respectively. The SLGNVM devices have 3V ~ 5V program/erase windows with good data retention and endurance properties. The arrays of SLGNVM devices are suitable for embedded EEPROM and flash in digital circuitries, and for the new applications of non-volatile-SRAM (nvSRAM), Non-Volatile-Register (NVR), and non-volatile FPGA (nvFPGA).
  • Keywords
    CMOS memory circuits; logic gates; random-access storage; CMOS logic process; NOR flash array; embedded EEPROM; nonvolatile FPGA; nonvolatile SRAM; nonvolatile register; scalable logic gate nonvolatile memory; size 110 nm; size 40 nm; size 55 nm; Arrays; CMOS integrated circuits; Logic gates; Nonvolatile memory; Programming; Registers; Threshold voltage; CMOS; Logic; Non-Volatile Memory; Scalable;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Non-Volatile Memory Technology Symposium (NVMTS), 2014 14th Annual
  • Print_ISBN
    978-1-4799-4203-9
  • Type

    conf

  • DOI
    10.1109/NVMTS.2014.7060846
  • Filename
    7060846