Title :
Impact of gate shapes on single event transients
Author :
Zhao Xinyuan ; Wang Liang ; Yue Suge
Author_Institution :
Beijing Microelectron. Technol. Inst., Beijing, China
Abstract :
3D-TCAD simulations in a 0.18um process are used to show the effect of gate shapes on the single event transients of both PMOS and NMOS. The results turn out that the SET pulse widths of enclosed layout transistors are much smaller than the standard layout transistors. The mechanisms and process that affect the charge collection of different layout structures are studied. Ssuggestions are made towards design guidelines and hardening approaches.
Keywords :
MOSFET; semiconductor device models; technology CAD (electronics); size 0.18 mum; CMOS integrated circuits; CMOS technology; Layout; Logic gates; Semiconductor device modeling; Standards; Transistors; SET; enclosed layout; parasitic bipolar transistor; pulse width;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061074
