DocumentCode
3578000
Title
A high performance solid-state storage system for high speed data acquisition applications
Author
Xujin Yu ; Xuguang Wang ; Wei Yan
Author_Institution
Solid-State Storage Joint Lab., Suzhou Inst. of Nano-Tech & Nano-Bionics, Suzhou, China
fYear
2014
Firstpage
1
Lastpage
2
Abstract
A FPGA based storage system with NAND flash array for high speed data acquisition applications is designed and implemented. A sharing bus architecture of flash arrays and a high performance flash controller that supports the new Open NAND Flash Interface Specification (ONFI) 3.0 standard are demonstrated. The total capacity of the storage system is 1 TB and the 16 channels of flash array can achieve a high bandwidth up to 1100 MB/s. The bit error rate of the system is analyzed.
Keywords
NAND circuits; data acquisition; error statistics; field programmable gate arrays; flash memories; FPGA based storage system; NAND flash array; ONFI 3.0 standard; bit error rate; flash controller; high speed data acquisition; open NAND flash interface specification; sharing bus architecture; solid-state storage system; Industries; Organizations; Registers; FPGA; NAND flash; bit error rate; data acquisition; flash controller;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
Type
conf
DOI
10.1109/EDSSC.2014.7061076
Filename
7061076
Link To Document