Title :
Improvement on ESD robustness of LDMOS by bulk and source interleaved dotting
Author :
Yang Wang ; Xiangliang Jin ; Acheng Zhou ; Liu Yang
Author_Institution :
Fac. of Mater., Optoelectron. & Phys., Xiangtan Univ., Xiangtan, China
Abstract :
Source and bulk layout style is investigated for the purpose of improving ESD performance of multi-fingered high-voltage (HV) LDMOS. The device with bulk and source interleaved dotting (BSDOT) is fabricated in a 0.5μm 24V CDMOS process. Its ESD characteristics are studied employing transmission line pulse (TLP) measurement. Compared to traditional gate grounded nLDMOS (GG-nLDMOS) with a total length of 400μm, the proposed device can effectively increase the secondary breakdown current (It2) from 2.43A to 5.55A without any extra chip area.
Keywords :
CMOS integrated circuits; MOS integrated circuits; electrostatic discharge; semiconductor device manufacture; ESD; bulk and source interleaved dotting; current 2.43 A to 5.55 A; gate grounded nLDMOS; size 0.5 mum; size 400 mum; source and bulk layout; transmission line pulse measurement; voltage 24 V; Artificial intelligence; Electrostatic discharges; Electrostatics; Layout; Robustness; Substrates; Bulk and source dotting; Current handling capability; Electrostatic discharge;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061086
