A 10-bit 100MS/s time domain Flash-SAR ADC

This paper presents a 10-bit subranging successive approximation register analog-to-digital converter (SAR ADC). A 3.5-bit time-domain coarse ADC converts the analog input to the time delay of two pulse signals and a time-to-digital converter (TDC) is used to quantize the delay. The coarse ADC controls the switching of the higher 3-bit capacitors in the digital-to-analog converter (DAC). A 7-bit SAR controls the remaining capacitors. The 1-bit redundancy corrects the linearity and mismatch error of the coarse ADC. The proposed 10-bit 100MS/s ADC is designed in a 65nm CMOS technology with 1.2V power supply. Simulation results show that this design achieves 59.7dB SNDR and consumes 2.69mW. The figure-of-merit (FoM) is 34.2fJ/conversion-step.