DocumentCode
3578041
Title
Data lane design for transmitter of 4.8Gbps serdes in 65nm CMOS
Author
Peng Wang ; Ziqiang Wang ; Chun Zhang ; Zhihua Wang
Author_Institution
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear
2014
Firstpage
1
Lastpage
2
Abstract
This paper presents a data lane circuit for transmitter of 4.8Gbps serdes in 65nm CMOS process. The data lane circuit mainly consists of 32:1 multiplexer (MUX) and equalizer. MUX adopts half-rate architecture and CMOS circuits to relax clock requirement and save power. The equalizer is a 4-tap feed forward equalizer (FFE) that can operate at two driving modes. Measurement shows that FFE can compensate over 7 dB channel loss at 4.8Gbps. And comparison of two modes is presented as design reference. The circuit´s area is 230×350 μm2.
Keywords
CMOS integrated circuits; equalisers; feedforward; integrated circuit design; multiplexing equipment; transmitters; CMOS process; channel loss; data lane circuit; driving modes; equalizer; feed forward equalizer; half-rate architecture; multiplexer; size 65 nm; transmitter; Laboratories; Multiplexing; Driving Modes; FFE; MUX;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
Type
conf
DOI
10.1109/EDSSC.2014.7061117
Filename
7061117
Link To Document