• DocumentCode
    3578049
  • Title

    Input ESD protection circuit design with special considerations for gate oxide protection in nanoscale technologies

  • Author

    Guangyi Lu ; Yuan Wang ; Jian Cao ; Song Jia ; Ganggang Zhang ; Xing Zhang

  • Author_Institution
    Key Lab. of Microelectron. Devices & Circuits (MoE), Peking Univ., Beijing, China
  • fYear
    2014
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    A novel input ESD protection circuit design is proposed in this paper. Voltage amplitude detection components are added into the novel design to effectively isolate gate oxide of input receiver from input pad to avoid voltage overshoots damage in ESD events while negligible signal degradation is maintained in normal data transmission.
  • Keywords
    electrostatic discharge; integrated circuit design; integrated circuit reliability; nanoelectronics; ESD protection circuit design; data transmission; gate oxide protection; nanoscale technologies; signal degradation; voltage amplitude detection components; voltage overshoots; Clamps; Data communication; Earth Observing System; Electrostatic discharges; Logic gates; Receivers; Transient analysis; Clamping Voltage; Electrostatic Discharge (ESD); Power-rail Clamp Circuit; Transmission Gate; Voltage Overshoot;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
  • Type

    conf

  • DOI
    10.1109/EDSSC.2014.7061125
  • Filename
    7061125
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3578049