A pipeline ADC with power-adaptable method for LTE

Author

Haijun Wu ; Bin Li

Author_Institution

Sch. of Electron. & Inf. Eng., South China Univ. of Technol., Guangzhou, China

fYear

2014

Firstpage

1

Lastpage

2

Abstract

In this paper, a power-adaptable method for LTE is proposed and applied to a pipeline analog-to-digital converter (ADC). A current adaptable generator was integrated in the chip to change the currents of the amplifiers and comparators by SPI. When the input frequency is 0.7 MHz and 1.5 MHz, D1D0 of interface control word is set to 00 and 01, then the current adaptable generator is 2 μA and 4 μA, respectively; When the input frequency is 10 MHz, D1D0 of interface control word is set to 11, then the current adaptable generator is 8 μA, then the converter can maintains the good performance and avoid an bit-error rate due to the quantization of ADC. The ADC fabricated in a 0.13 μm CMOS process. The measured DNL and INL are +0.4/-0.43LSB and +0.67/-0.91LSB. SFDR and SNDR are 65.3 dB and 52.4 dB, respectively.

Keywords

CMOS integrated circuits; Long Term Evolution; analogue-digital conversion; error statistics; ADC; CMOS; LTE; SPI; bit-error rate; current 2 muA; current 4 muA; current 8 muA; current adaptable generator; frequency 0.7 MHz; frequency 1.5 MHz; frequency 10 MHz; pipeline analog-to-digital converter; size 0.13 mum; Bit error rate; CMOS integrated circuits; Pipelines; Switches; CMOS; LTE; Pipeline ADC; Transceiver; switched capacitor;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on

Type

conf

DOI

10.1109/EDSSC.2014.7061132

Filename

7061132