Title :
A 14b continuous-time delta-sigma modulator with 2MHz signal bandwidth
Author :
Yibin Wang ; Chenxi Han ; Dongmei Li ; Zhihua Wang
Author_Institution :
Dept. of Electron. Eng., Tsinghua Univ., Beijing, China
Abstract :
A 14-bit 10mW 2MHz BW continuous-time (CT) ΔΣ modulator, implemented in UMC 180nm process, is presented in this paper. High-speed high-resolution low-noise dynamic latch comparator is designed for quantization. A low-latency dynamic element matching (DEM) module is included in consideration of nonlinear mismatching of DAC units. RPI introduces direct feedforward path around the quantizer to compensate for excess loop delay (ELD), which is more efficient in power and area compared to conventional structure. The post-layout simulation achieves a SNDR of 79dB with a FOM of 350fJ/conv-step and occupies 0.1mm2 active area.
Keywords :
CMOS digital integrated circuits; comparators (circuits); continuous time systems; delta-sigma modulation; feedforward; BW continuous-time ΔΣ modulator; DAC units; ELD; RPI; continuous-time delta-sigma modulator; direct feedforward path; excess loop delay; frequency 2 MHz; high-speed high-resolution low-noise dynamic latch comparator; low-latency DEM module; low-latency dynamic element matching module; nonlinear mismatching; power 10 mW; quantization; size 180 nm; word length 14 bit; Bandwidth; Clocks; Feedforward neural networks; Layout; Modulation; Resistance; Resistors;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061139
