Title :
A novel 4-bit sub-ranging delay-line based ADC for DC-DC converter
Author :
Lixing Gong ; Weixin Gai
Author_Institution :
Inst. of Microelectron., Peking Univ., Beijing, China
Abstract :
This paper presents a novel sub-ranging delay-line based analogue to digital converter (ADC) for DC-DC converter. The proposed ADC utilizes both rising and falling edge of the delay line to respectively perform coarse and fine quantization. A 4-bit 100MHz ADC employing the novel sub-ranging analogue-to-digital conversion was implemented in 0.18-μm CMOS process. The estimated area is approximately 37% smaller and power consumption is 1.46mW.
Keywords :
CMOS integrated circuits; DC-DC power convertors; delay lines; power consumption; quantisation (signal); 4-bit subranging delay-line based ADC; CMOS process; DC-DC converter; fine quantization; power 1.46 mW; power consumption; size 0.18 mum; subranging delay-line based analogue to digital converter; Ear; DCDC converter; delay cell; delay-line based ADC; sub-range;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061151
