A clock calibration method for an all-digital burst-mode CDR with embedded TDC

Author

Baoguang Liu ; Yuan Wang ; Song Jia ; Ganggang Zhang ; Xing Zhang

Author_Institution

Key Lab. of Microelectron. Devices & Circuits, Peking Univ., Beijing, China

fYear

2014

Firstpage

1

Lastpage

2

Abstract

This paper presents a novel calibration method for an all-digital burst-mode clock and data recovery (BM-CDR) with embedded time-to-digital converter (TDC). The proposed method ensures the TDC-embedded Phase Generator to get the precise delays outside of Shared Delay Line, which makes the measured period more exactly. This method operates at 1.25Gbps. Compared with the BM-CDR without calibration, the proposed method reduces the clock jitter from 221.58ps to 98.11ps, about 55.72% under a 5-bit consecutive identical digits.

Keywords

calibration; clock and data recovery circuits; clocks; embedded systems; jitter; time-digital conversion; TDC-embedded phase generator; all-digital burst-mode CDR; all-digital burst-mode clock and data recovery; bit rate 1.25 Gbit/s; calibration method for an; shared delay line; time 221.58 ps to 98.11 ps; time-to-digital converter; word length 5 bit; Clocks; Generators; Image edge detection; Clock Calibration; Time-to-Digital Converter (TDC); clock and data recovery (CDR);

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on

Type

conf

DOI

10.1109/EDSSC.2014.7061159

Filename

7061159