FPGA prototyping for CORDIC-based OFDM baseband receiver

In this paper, a FPGA prototyping of CORDIC-based OFDM baseband receiver is presented to demonstrate the joint carrier synchronization and channel equalization algorithm. The versatile arithmetics of CORDIC are employed to realize various baseband operations, including gain adjustment, phase compensation, initial gain/phase estimation and derotator. The maximum uncoded data rate of the FPGA prototyping is 72 Mbps for 64-QAM modulation. The measured EVM for given SNR=26 dB and 64-QAM is -31 dB. The physical design shows that the core area is 1.2 mm² with 0.18 μm CMOS technology. The core power consumption is 33.2 mW with 1.8 V supply voltage and 40 MHz operating clock.