A 10Gb/s source-synchronous transmitter in 65nm CMOS technology

This paper describes the design of a source-synchronous transmitter in 65nm CMOS technology. The transmitter consists of five data lanes plus one forwarded clock lane. Every single lane works at 10Gb/s. The clock distribution path is carefully designed to ensure the synchronous of the divided clock in every data lane. And this design is power efficient by optimizing the structure of MUX. Furthermore, a 3 tap feed forward equalizer (FFE) is applied to the driver to compensate channel loss. The experiment result shows that, the output peak-to-peak jitter is 50ps when the transmitter delivers 10Gb/s PRBS7 data over a channel which has a loss of 12.3dB at 5GHz. The power consumption of this circuit is 6.1mW/Gbps for 1.2V supply and the chip area is 1.2mm².