A 10Gb/s speculative decision feedback equalizer with a novel implementation of adaption in 65nm CMOS technology

Author

Shuai Yuan ; Ziqiang Wang ; Xuqiang Zheng ; Liji Wu ; Chun Zhang ; Zhihua Wang

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2014

Firstpage

1

Lastpage

2

Abstract

A 10Gb/s half-rate adaptive 1-tap speculative decision feedback equalizer (DFE) is implemented in 65nm CMOS. Adaption of the DFE is achieved by using a novel mixed-signal implementation of the sign-sign least mean square (SS-LMS) algorithm to continuously adapt the coefficient of the unique tap. The simulation results show that the DFE can totally compensate 16.2dB loss at the Nyquist frequency for 10Gb/s PRBS31 transmission over 700mm RLGC (resistance, inductance, conductance and capacitance) channel. The active layout area is 0.01 mm² and total power consumption is 24mW for 1.2V supply.

Keywords

decision feedback equalisers; least mean squares methods; CMOS technology; DFE adaption; Nyquist frequency; PRBS31 transmission; RLGC channel; SS-LMS algorithm; active layout area; bit rate 10 Gbit/s; half-rate adaptive 1-tap speculative DFE; loss 16.2 dB; loss compensation; mixed-signal implementation; power 24 mW; resistance-inductance-conductance-capacitance channel; sign-sign least mean square algorithm; size 65 nm; speculative decision feedback equalizer; total power consumption; voltage 1.2 V; CMOS integrated circuits; CMOS technology; Decision feedback equalizers; IP networks; Least squares approximations;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on

Type

conf

DOI

10.1109/EDSSC.2014.7061178

Filename

7061178