Backside silicon-embedded inductor using porous silicon layer for substrate effect suppression

In this paper, a backside silicon-embedded inductor (BSEI) using a porous silicon (PS) layer is proposed and studied for substrate effect suppression. The PS layer has a lower effective permittivity and a much higher effective resistivity than the silicon substrate, and therefore can form a good insulation layer to suppress the capacitive substrate effect. With the PS layer, the peak quality factor of a 1-mm² BSEI can be increased from 6.2 to over 11 for a PS layer thickness of 40 μm, with the operating frequency increased from around 70 MHz to over 200 MHz. This makes the BSEI more promising for power supply-on-chip applications.