Novel comparator integrated charge pump phased locked loop to eliminate start-up issue

Noise coupling at various nodes within the loop during start-up is one of the reasons that make PLL not to start-up or lock within specified lock time. Therefore a robust PLL design is required to counter these effects of noise. In this paper the novel comparator integrated charge pump PLL is discussed. Simulation and characterization were performed to observe the integrated PLL behavior across voltage and temperature. The programmable PLL was designed for reference input clock of 10 to 30MHz and maximum output frequency of 100MHz. Internal nodes of the chip were probed to observe the behavior of individual blocks (Comparator, Phase frequency detector, Charge pump, VCO and P/Q dividers) of the integrated charge pump PLL chip. Comparing the characteristics with the conventional PLL, the proposed PLL showed no lock time and start-up issue in the presence of noise at VCO output and feedback dividers.