A novel hybrid storage architecture for nonvolatile FPGA

High leakage power becomes an important factor hindering the deployment of FPGA (Field Programmable Gate Array) in portable devices. Emerging nonvolatile memory technologies can keep data with zero standby power and are promising for configurable memory in low power FPGAs. However, simple replacement of SRAM (Static Random Access Memory) with nonvolatile memory may increase tile area and delay significantly. This paper proposes an area efficient hybrid storage architecture for FeRAM(Ferroelectric Random Access Memory) based nonvolatile FPGA. We also discuss the tradeoff between tile area and configuration time in the hybrid storage system. The proposed design reduces the silicon area by 7.2 times compared with the previous FeRAM based FPGA and makes the nonvolatile tile area similar to the value in volatile SRAM based FPGAs.