Load-transient enhanced low-dropout regulator based on buffer stage with paralleled current and voltage paths for low-ESR applications

A load-transient enhanced low-dropout regulator (LDR) based on a buffer stage with paralleled current and voltage paths is proposed. By using a 1.2V p-type source-follower with small bias current as the voltage path, the gate-swing of the power transistor is widened and load capability is enhanced significantly. Moreover, by adding an inverting amplifier with diode-connected load as the current path, the LDR has good loop stability and fast load transient response. The proposed LDR was designed in a 0.13 μm mixed-mode CMOS process. The dropout voltage is 0.2V, and the quiescent current is only 10uA. Simulation results show that the LDR is stable with zero-ESR compensation, and it achieves 11mV voltage dip for a load current step of 200mA with 1ns edge times.