DocumentCode
3578179
Title
Gate stress study on High Voltage MOSFET for Non-Volatile Memory applications
Author
Carmona, M. ; Lopez, L. ; Ogier, J.-L. ; Goguenheim, D.
Author_Institution
STMicroelectron., Rousset, France
fYear
2014
Firstpage
1
Lastpage
2
Abstract
In this paper, gate stress has been studied on High Voltage p- and n-MOSFETs used for Non-Volatile Memory applications. For the first time, a higher degradation on n-channel transistor compared to p-channel transistor has been observed. Time dependence, recovery effect, voltage acceleration factor and activation energy have been evaluated.
Keywords
MOSFET; MOSFET circuits; random-access storage; activation energy; gate stress study; high-voltage p-n MOSFET; n-channel transistor degradation; nonvolatile memory application; recovery effect; time dependence; voltage acceleration factor; Degradation; Logic gates; MOSFET; MOSFET circuits; Semiconductor device modeling; Stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
Type
conf
DOI
10.1109/EDSSC.2014.7061255
Filename
7061255
Link To Document