Title :
High-speed and low-power FRAM with a bitline-segmental array
Author :
Ze Jia ; Jizhi Liu ; Zihao Tao ; Zhiwei Liu ; Liou, Juin J. ; Haiyang Liu ; Wei Yang ; Junfeng Zhao
Author_Institution :
Sch. of Microelectron. & Solid-State Electron., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
Abstract :
A bitline-segmental array architecture for ferroelectric random access memory (FRAM) is proposed to achieve lower power consumption and higher operation speed, in which the cell array is divided into four local blocks. Compared to the conventional array, the bitline-segmental arrays can decrease the power consumption by about 53 percent and 55 percent for read and write operation respectively. An experimental prototype utilizing the proposed architecture is implemented in 0.35 μ m 3-metal process and functionally verified.
Keywords :
ferroelectric storage; low-power electronics; power consumption; random-access storage; 3-metal process; FRAM; bitline-segmental array architecture; cell array; ferroelectric random access memory; local blocks; power consumption; read operation; size 0.53 mum; write operation; Ferroelectric films; Nonvolatile memory; Random access memory; FRAM; array; bitline-segmental; power consumption; speed;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061266
