Title :
Slew rate improved 2×VDD output buffer using leakage and delay compensation
Author :
Tzung-Je Lee ; Wei Lin ; Chua-Chin Wang
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Cheng Shiu Univ., Kaohsiung, Taiwan
Abstract :
A slew rate improved 2×VDD output buffer is proposed in the paper. By using the leakage compensation circuit, the gate oxide overstress at the output stage is avoided and the rising SR is improved. Besides, by using the Delay Buffer, the falling SR is improved by avoiding the PMOS and NMOS transistors turned on at the same time. The proposed design is carried out using a typical 90 nm CMOS process. After the leakage and delay compensation, the SR of the rising and falling edge of the output signal for VDDIO = 1.8 V is improved 27% and 22%, respectively. The maximum data rate is simulated to be 330/500 MHz for VDDIO = 1.8/1.0 V, respectively.
Keywords :
CMOS integrated circuits; delays; electrical faults; CMOS process; delay buffer; delay compensation; gate oxide overstressing; leakage compensation circuit; size 90 nm; slew rate improvement; voltage 1 V; voltage 1.8 V; CMOS process; Computers; Generators; Logic gates; MOS devices; Transient analysis; Transistors; gate oxide overstress; leakage compensation; mixed-voltage;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061267
