Title :
Comparative analysis of flip-flops in sub- and near-threshold operations
Author :
Jinn-Shyan Wang ; Shih-Nung Wei
Author_Institution :
Dept. of EE, Nat. Chung-Cheng Univ., Chiayi, Taiwan
Abstract :
The results of a comparative study of four flip-flops (FFs) for sub-threshold and near-threshold designs are presented. All FFs are firstly designed in 0.3V 65nm CMOS technology with the same in/out constraints. Process variations are considered, and Monte Carlo simulations are used to check the suitability of different timing definitions for low-voltage operations. According to the suitable definition, delay time, active energy, and leakage power at 0.3V and 0.5V are used as comparison indices of FFs.
Keywords :
CMOS logic circuits; delays; electrical faults; flip-flops; logic design; CMOS technology; Monte Carlo simulations; active energy; delay time; flip-flops; leakage power; low-voltage operations; nearthreshold operation; process variations; size 65 nm; subthreshold operation; timing definitions; voltage 0.3 V; voltage 0.5 V; CMOS integrated circuits; Delays; Flip-flops; Monte Carlo methods; System-on-chip; Transistors; flip-flop; low voltage; near-threshold; sub-threshold;
Conference_Titel :
Electron Devices and Solid-State Circuits (EDSSC), 2014 IEEE International Conference on
DOI :
10.1109/EDSSC.2014.7061281
