Performance analysis of maximum likelihood arrangement in the receiver structure for LTE PCFICH aiming at low resource utilization using VLSI DSP techniques

In Long Term Evolution (LTE) downlink systems, the Physical Control Format Indicator Channel (PCFICH) carries the control information about the number of Orthogonal Frequency Division Multiplexing (OFDM) symbols used for transmission of control information. In this paper, receiver structure using argument maximum in maximum likelihood (ML) algorithm that utilizes less hardware are proposed and implemented for decoding the CFI value. The proposed architectures are implemented in Virtex-6 xc6vlx240tff1156-1 FPGA device for various antenna configurations at base station and User Equipment (UE). The performance of the proposed architectures is analyzed and compared with the architecture already designed using argument minimum and direct methods in terms of timing cycles and resource complexity. It is shown that the proposed architectures use fewer amounts of hardware resources in FPGA compared to other methods.