Implementation of pipelined hardware architecture for AES algorithm using FPGA

The Advanced Encryption Standard is the recent data security standard referred to as Federal Information Processing Standard 197 (FIPS 197) acquired worldwide by several private and public sectors for protective needs of data storage and secure data application from mobile consumer products to high end user. Most of the AES implementation for reconfigurable devices, however based on the configurable logic such as flip-flops and lookup tables. In this paper AES implementation focuas on embedded function inside of Xilinx devices such as large dual ported BRAM and DSP blocks with the goal of minimizing the use of register and lookup tables that those may be used for other functions. The paper presents a hardware implementation of AES algorithm on FPGA. The proposed model of AES algorithm was implemented in FPGA using Virtex 5 kit and Xilinx ISE development suite.