New power gated SRAM cell in 90nm CMOS technology with low leakage current and high data stability for sleep mode

Static Random Access Memory (SRAM) is the most popular circuit which is used in all processors and occupies the considerable area of the chip. The total power consumption of circuit is largely dependent on power dissipated by memory. There were several efforts for reduction in power consumption such as Power Gated SRAM circuits and increasing virtual ground voltage. The previous techniques were capable to have either high data stability or low leakage current. The paper presents an implementation of a New Power Gated technique which is used to have low leakage current for sleep mode. It also helps to enhance the Static Noise Margin (SNM). Data stability, leakage current, write margin and power consumption are calculated and compared among conventional 6T SRAM, Old Power Gated SRAM and New Power Gated SRAM circuits. All the results are implemented in 90nm CMOS technology using HSPICE tools.