SCPG: A new technique to reduce leakage power in 16-bit binary multiplier

Power gating is the most effective existing solution to reduce leakage power for VLSI Logic. Though, power gating is not basically working in an active mode due to the expenses of inflow current and data detainment. The proposed SCPG (Subclass power gating) technique in this paper brings synchronously with scaling of voltage and frequency and reduction of power is acquired by power gating in the clock cycle throughout active mode, to decrease overall power expenditure by power gating within the clock cycle. The proposed SCPG technique can be enforce using standard EDA tools with simple modification to the standard power gating design flow. Adopting a 90nm library and the Synopsys EDA tool suite, the technique is to validate with 16-bit parallel binary multiplier. Compared to designs with SCPG, in a given power budget, we prove that 50× increase in clock frequency with 45× improvement in energy efficiency in 16 bit parallel binary multiplier.