An FPGA-based multi-core system for synthetic aperture radar data processing

Author

Ning Hou ; Duoli Zhang ; Gaoming Du ; Yukun Song

Author_Institution

Coll. of Electr. & Inf. Eng., Henan Univ. of Urban Constr., Pingdingshan, China

fYear

2014

Firstpage

1

Lastpage

4

Abstract

Often graphic processing units (GPGPUs) are used for data processing as the range-Doppler algorithm is computationally expensive and highly parallel. However, GPGPUs may not be an appropriate solution for applications with strictly constrained space and power requirements. In this paper, we implemented a FPGA-based multi-core system for SAR data processing with Range-Doppler algorithm. Our system consists of 4 Xilinx Virtex-6-550T devices with speed grade -1 and several off-chip memory devices. We design a scalable multi-core processor consisting of 16 processing elements and a 2D-Mesh network-on-chip on the FPGAs. Our system calculates real-time SAR raw data in pipeline, and can acquire a 256 level gray SAR images containing 2048×4096 pixels in 12.03 second at the speed of 130MHz. We measure the power of the whole system is about 85 watt.

Keywords

Doppler radar; field programmable gate arrays; graphics processing units; network-on-chip; radar imaging; synthetic aperture radar; 2D-mesh network-on-chip; FPGA; SAR images; Xilinx Virtex-6-550T devices; frequency 130 MHz; graphic processing units; multi-core system; off-chip memory devices; range-Doppler algorithm; synthetic aperture radar data processing; Algorithm design and analysis; Computational modeling; Data processing; Field programmable gate arrays; Network-on-chip; Signal processing algorithms; Synthetic aperture radar; FPGA; Network on Chip; SAR; multi-core chipset;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-counterfeiting, Security, and Identification (ASID), 2014 International Conference on

Print_ISBN

978-1-4799-7117-6

Type

conf

DOI

10.1109/ICASID.2014.7064956

Filename

7064956