Designing a precision comparator for 10-bit synchronization SAR ADC

A precision comparator applied to a 10-bit synchronization successive approximation analog-to-digital converter (SAR ADC) is presented in this paper. The differential structure of the preamplifier circuit improves the accuracy of the input signal, and its isolation effect reduces the effect of kickback noise and latch offset voltage. Two level of dynamic latch circuit effectively improves the speed of the comparator. Output buffer circuit increases the drive ability of the output stage and adjusts the output waveform. The comparator has the characteristics of high precision and low power dissipation. Realized using SMIC 65nm CMOS process technology, at the voltage supply of 2.5V and 2MHz sampling frequency, simulation results show that the resolution of the precision comparator is 0.5425mV, offset voltage is 1.40uV and static power dissipation is 63uW.