Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGA

This paper, deals with Latch Free Clock Gating technique for reduction of clock power and total power consumption in Low Power Arithmetic and Logic Unit and we have analysed power reduction on different FPGA devices. Without latch free clock gating technique in Low Power Arithmetic and Logic Unit the Contribution of Clock power was 39mW in Virtex-6 FPGA, 14mW in Virtex-5 FPGA, 24mW in Virtex-4 FPGA, 18mW in Spartan-3 FPGA, 18mW in Spartan-3E FPGA, 18mW in Spartan-6 FPGA, 5mW in Artix-7 FPGA of total power when device is operating at frequency of 1GHz. After implementation of latch free clock gating technique in Low Power Arithmetic and Logic Unit, Clock power contribution is 3mW in Virtex-6 FPGA, 5mW in Virtex-5 FPGA, 8mW in Virtex-4 FPGA, 5mW in Spartan-3 FPGA, 9mW in Spartan-3E FPGA, 7mW in Spartan-6 FPGA, 2mW in Artix-7 FPGA in total power. Total Power consumption is reduces to 1.41%, 1.33%, 2.53%, 7.65%, 2.88%, 3.38% and 2.64% on 40-nm Virtex-6, 65-nm Virtex-5, 90-nm Virtex-4, Spartan 3, Spartan 3E, Spartan-6 and Artix-7 target device respectively with device operating frequency is 1GHz. There is 92.31%, 64.29%, 66.67%, 72.22%, 50%, 61.11% and 60% reduction in clock power on 40-nm Virtex-6, 65-nm Virtex-5, 90-nm Virtex 4, Spartan 3, Spartan 3E, Spartan-6 and Artix-7 target device respectively with device operating frequency is 1GHz.