Title :
Low Power High Performance ROM Design on FPGA Using LVDCI I/O Standard
Author :
Saini, Rishita ; Bansal, Neha ; Bansal, Meenakshi ; Pandey, Bishwajeet ; Kalra, Lakshay
Author_Institution :
Res. & Innovation Network, Chitkara Univ., Rajpura, India
Abstract :
In this work, we are using LVDCI I/O standard in energy efficient ROM design on FPGA. There is a 92% reduction in clock power, 50% reduction in signal power, 32-46% reduction in IO´s power, and 25-27% reduction in total power, when we scale down frequency from 4.0GHz to 1.0GHz. There is no reduction in clock power and signal power, when we change I/O standard from LVDCI 25 to LVDCI 15, but there is reduction of 61-69% of IO´s power and reduction of 16-18% in total power. This design is implemented on Virtex-5 FPGA using Verilog hardware description language and Xilinx ISE simulator. LVDCI 15, LVDCI 18, LVDCI 25, HSLVDCI 15 and HSLVDCI 18 are five different IO standard is in use to design energy efficient ROM. LV stands for Low Voltage, HS means High Speed and DCI means Digitally Control impedance.
Keywords :
field programmable gate arrays; integrated circuit design; low-power electronics; read-only storage; LVDCI I/O standard; Verilog hardware description language; Virtex-5 FPGA; Xilinx ISE simulator; clock power reduction; energy efficient ROM design; frequency 4.0 GHz to 1.0 GHz; low power high performance ROM design; low voltage digitally control impedance; signal power reduction; Clocks; Energy efficiency; Field programmable gate arrays; Power dissipation; Random access memory; Read only memory; Standards; Energy Efficient Design; FPGA; High Performance; I/O standard; I/Os Power; LVDCI; ROM;
Conference_Titel :
Computational Intelligence and Communication Networks (CICN), 2014 International Conference on
Print_ISBN :
978-1-4799-6928-9
DOI :
10.1109/CICN.2014.197
