Design of High Frequency and Energy Efficient 3D Frame Buffer on 40 nm FPGA

In this paper, we have proposed the design of energy efficient and high frequency frame buffer on 40 nm FPGA. The operational frequency of buffer is kept quite high of 1THz and it has been recorded that we need to optimize power considerations in order to reduce the power consumption. The values are recorded on LVCMOS and LVDCI. For LVCMOS, we recorded that average power consumed is 88W and for LVDCI the average power consumed is 76W. In the later stage we observe that with using the technique of clock gating the power consumption with LVCMOS reduced to 52W and for LVDCI the power consumption is reduced much to 45W. This has also been observed that LVDCI reduces the IOs power more than LVCMOS. For LVCMOS the reading is of IOs is 21W and for LVDCI it is 9W.