Title :
Design of High Frequency and Energy Efficient 3D Frame Buffer on 40 nm FPGA
Author :
Kaur, Karandeep ; Ghuman, Gurpinder Singh ; Kaur, Tarandeep
Author_Institution :
Electron. & Commun. Eng., Chitkara Univ., Chandigarh, India
Abstract :
In this paper, we have proposed the design of energy efficient and high frequency frame buffer on 40 nm FPGA. The operational frequency of buffer is kept quite high of 1THz and it has been recorded that we need to optimize power considerations in order to reduce the power consumption. The values are recorded on LVCMOS and LVDCI. For LVCMOS, we recorded that average power consumed is 88W and for LVDCI the average power consumed is 76W. In the later stage we observe that with using the technique of clock gating the power consumption with LVCMOS reduced to 52W and for LVDCI the power consumption is reduced much to 45W. This has also been observed that LVDCI reduces the IOs power more than LVCMOS. For LVCMOS the reading is of IOs is 21W and for LVDCI it is 9W.
Keywords :
CMOS logic circuits; buffer circuits; field programmable gate arrays; power consumption; FPGA; LVCMOS; LVDCI; clock gating technique; energy efficient 3D frame buffer; high frequency 3D frame buffer; operational frequency; power 21 W; power 9 W; power consumption; size 40 nm; Clocks; Digital signal processing; Energy efficiency; Field programmable gate arrays; Logic gates; Power demand; Standards; Clock gating; Energy efficient frame buffer; FPGA; LVCMOS; LVDCI;
Conference_Titel :
Computational Intelligence and Communication Networks (CICN), 2014 International Conference on
Print_ISBN :
978-1-4799-6928-9
DOI :
10.1109/CICN.2014.199
