Low Voltage Digitally Controlled Impedance Based Energy Efficient Vedic Multiplier Design on 28nm FPGA

Low Voltage Digitally Controlled Impedance (LVDCI) is an I/O standard available on FPGA. This design is LVDCI IO standard based Energy Efficient Vedic Multiplier Design on FPGA. Selection of IO standard play an important role in power dissipation of design. Therefore, we are going to select the most energy efficient IO standards in LVDCI family for Vedic Multiplier. This Vedic multiplier design is a part of project of Vedic arithmetic circuits. The final deliverable of this project is Vedic Processor by merging both concepts of Veda, first book of this world, and the latest technology of this world. In order to test thermal aware design, we want to see that how does an electronic device behave if we change the temperature of surrounding in which it is working. For that purpose we have taken temperatures of four different regions. Furnace Creek Ranch is area of North America recorded the highest temperature of the world that is 56.7°C [1]. Approximately, 53.5°C is the maximum temperature recorded in Mohenjo-Daro situated in Sindh Pakistan [1]. We have also taken median temperature of Delhi i.e. 40°C and standard normal temperature i.e. 21°C. We are operating Vedic Multiplier with the four different temperature and different LVDCI IO standard and observe device performance, and power dissipation. When we use 28nm FPGA under room temperature of 40°C, there are 93.42%, 92.6%, 93.99%, 93.59% and 89.79% reduction in total power dissipation of Vedic multiplier using LVDCI 15, LVDCI 18, LVDCI DV2 15, LVDCI DV2 18 and HSLVDCI 15 respectively. Similarly, when we use 28nm FPGA, there is approximately 90-96% reduction in leakage power dissipation of Vedic multiplier using different LVDCI and different temperature. There is no change in I/O power with change in temperature for uniform IO standard. When we use different IO standard of LVDCI family, there is significant reduction in leakage power. FPGA based on 28 nm technology is more ener- y efficient than 40 nm technology based FPGA.