Power Optimization of Sequential Circuit Based ALU Using Gated Clock & Pulse Enable Logic

The main aim of this work is to study and show power reduction by using clock gating techniques with pulse enable concept. In this two 8 bit input data and a MUX 4:1 for selection of instruction which is a combination of logic and arithmetic operation´s and total of 11 instruction are performed in the proposed design. This technique is applied on the D Flip-Flop based gated clock ALU & negative latch based gated ALU at RTL level. At different operating frequency 100MHZ, 200MHZ, 300MHZ, 500MHZ, 700MHZ, the percentage of dissipated power 1.02%, 1.15%, 1.24%, 1.49%, 1.63% respectively reduced in negative latch based gated clock ALU with respect to D flip-flop based gated clock ALU. The percentage of reduction is achieved in 1ns, 2ns, 3ns, 5ns, and 10ns clock period respectively. This paper is focused on the optimization of power by implementing pulse enable gated clock, after doing the operation by arithmetic and logic unit through gated clock approach, consumed power is slightly greater than the required power which is used to generate in gated clock signal. Xilinx 14.2 has been used as ISE in which vertex 6 is 40nm technology FPGA, 1 volt with Xc6vlx240t family. The negative flip flop is best for this design as less number of gate counts and also area is less.