Real-time SoC architecture and implementation for Variable Speech PDF based noise cancellation system

This paper discusses the architecture and implementation of system-on-chip (SoC) for noise cancellation system which uses Variable Speech PDF and MAP Estimation as noise cancelling algorithm. The hardware software co-design approach is used to achieve real-time performance while considering ease of implementation and design flexibility. The software module utilizes LEON SPARC-v8 and FPU co-prosessor as processing unit. The AMBA based Hanning Filter and FFT/IFFT are designed as processing accelerator module to increase system performance. The FFT/IFFT module uses custom Radix-2² Single Delay Feedback (R2²SDF). In order to provide high data transfer rate between buffer and hardware accelerators, the DMA controller is also designed. The overall system implementation utilizes 18,500 logic elements and uses 21.87 kB of memory. Latency of the system is 0.69 ms so the system can be run in real-time. The system is implemented on FPGA Altera DE2-70 with both algorithms and the noise cancellation function has been verified.