LASCA-interconnect parasitic extraction tool for deep-submicron IC design

Author

Ferreira, Fabio Klein ; Moraes, Fernando ; Reis, Ricardo

Author_Institution

Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil

fYear

2000

fDate

2000

Firstpage

327

Lastpage

332

Abstract

A fast capacitance and resistance extraction tool (wire extractor) is presented. Five models are implemented: ground capacitances, ground plus coupling capacitances and RC models (L, π and T lumped). The designer can choose one of these models according some criteria, such as accuracy, CPU time and circuit complexity. Comparisons between our wire extractor and Diva extractor (Cadence Design Systems) for C models, give an average difference of only 5% in the final delay of some benchmarks, being up to 30 times faster than Diva

Keywords

VLSI; capacitance; circuit complexity; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; C models; CPU time; Diva extractor comparison; LASCA tool; RC models; VLSI; bin-based algorithm; circuit complexity; connectivity extraction; deep-submicron IC design; fast capacitance and resistance extraction; ground capacitances; ground plus coupling capacitances; interconnect parasitic extraction tool; layout extraction; polygon distribution; virtual grid; wire extractor; Aluminum; Central Processing Unit; Coupling circuits; Delay; Design automation; Electronics industry; Integrated circuit interconnections; Integrated circuit technology; Parasitic capacitance; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2000. Proceedings. 13th Symposium on

Conference_Location

Manaus

Print_ISBN

0-7695-0843-X

Type

conf

DOI

10.1109/SBCCI.2000.876050

Filename

876050