A CMOS T/R switch using a MOSFET diode pair for linearity improvement

This paper describes a novel CMOS T/R switch topology scheme. The proposed scheme facilitates the diode connected transistor pair in realizing a high power handling off-transistor and suppressing the channel forming signal to elevate IIP3 and input P1dB performance. The prototype without additional LC components and negative control voltage allows for the miniaturized integration of the T/R switch in a CMOS System on chip circuit. Finally, design examples fabricated with 0.18µm CMOS technology demonstrate a 22.4dBm Pin1dB and 33dBm IIP3 performance to prove the effectiveness of the proposed switch configuration.