Design of low-power high-speed divide-by-2/3 prescalers with improved true single-phase clock scheme

New design improvement aiming to reduce the power consumption of true single-phase clock-based dual-modulus divide-by-2/3 prescalers is presented. The first latch stages of TSPC FFs are merged to reduce power and capacitance. Also, a pass transistor is introduced to cut off short circuit current. Hspice simulation of the proposed scheme in 40nm process demonstrates best power efficiency and power-delay-product among referenced designs. Besides, it shows comparable speed with extended TSPC prescalers.