Title :
A 500 MS/s 6 bits delay line ADC with inherit sample & hold
Author :
Hassan, Ali H. ; Ali, Maged ; Mohammed, Nabil ; Ali, Ahmed ; Hassoubh, Mohammed ; Ismail, M. Wagih ; Refky, Mohammed ; Mostafa, Hassan
Author_Institution :
Electron. & Commun. Eng. Dept., Cairo Univ., Giza, Egypt
Abstract :
Analog-to-Digital Converters (ADCs) are essential blocks in digital signal processing systems, software defined radio receivers, and biomedical systems. This paper introduces a 6-bit Delay Line based Analog to Digital Converter (DL-ADC). This DL-ADC utilizes an inherited sample and hold technique to eliminate the dedicated power hungry sample and hold circuit. A prototype of the proposed DL-ADC is implemented in 65nm CMOS technology, where it consumes 1.8 mW and achieves a maximum SNDR of 35.5 dB with sampling rate 500 MHZ with a corresponding Figure of Merit (FOM) of 74.22 fJ/step.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; delay lines; sample and hold circuits; CMOS technology; DL-ADC; FOM; biomedical systems; delay line based analog to digital converter; digital signal processing systems; figure of merit; frequency 500 MHz; inherit sample & hold circuits; power 1.8 mW; power hungry sample and hold circuit; size 65 nm; software defined radio receivers; word length 6 bit; Analog-digital conversion; CMOS integrated circuits; CMOS technology; Clocks; Delay lines; Delays; Receivers; CMOS Technology Scaling Down; Delay Line; Inherit sample and hold; Time-Based ADC; UWB receivers;
Conference_Titel :
Microelectronics (ICM), 2014 26th International Conference on
DOI :
10.1109/ICM.2014.7071815
