Optimized hardware architecture for implementing IEEE 754 standard double precision floating point adder/subtractor

IEEE 754 standard double precision (64-bit) binary floating point arithmetic unit is often necessary in complex digital signal processing applications. The basic operations, floating point addition and subtraction, need to be optimized to efficiently compute floating point multiplier, divider and square root. However, the main challenge is to design the floating point arithmetic unit hardware that uses fewer logical resources of FPGA and ASIC and has a maximum operating frequency with a fewer number of clock cycles. This paper proposes a new, efficient hardware design methodology for implementing double precision floating point addition and subtraction. The pipeline hardware design is implemented on Virtex-6 and Virtex-5 Xilinx FPGA. As per the synthesis result, the maximum operating frequency achieved for the proposed hardware design for clock latency of 8 cycles is significantly higher than the previous hardware designs. Furthermore, area overhead is 50 percent fewer than that of the earlier proposed hardware designs for computing IEEE 754 compliant double precision floating point addition and subtraction.