DocumentCode
3583304
Title
On input permutation technique for multiple-valued logic synthesis
Author
Hata, Yutaka ; Kamiura, Naotake ; Yamato, Kazuharu
Author_Institution
Dept. of Comput. Eng., Himeji Inst. of Technol., Japan
fYear
1995
Firstpage
170
Lastpage
175
Abstract
An input permutation technique with respect to multiple valued logic synthesis is introduced. First, it is applied to multiple valued sum of products expressions where sum refers to TSUM. Some upper bounds are clarified on the number of implicants in minimal sum of products expressions for one variable and two variable functions with permuted logic values. An experiment was done on randomly generated functions. The result shows that we can have a saving of approximately 15% on the average by permuting input values. Next, we compare the input permutation with output permutation. As a result, input permutation and output permutation yield a similar saving rate of implicants and output permutation has an advantage of hardware cost and minimization times. Moreover, we show that the use of input permutation for multiple valued sum of products expressions with window literals yields similar results when one uses sum of products expressions with set literals
Keywords
logic design; multivalued logic; set theory; TSUM; input permutation; input permutation technique; minimal sum of products expressions; minimization times; multiple valued sum of products expressions; multiple-valued logic synthesis; output permutation; permuted logic values; randomly generated functions; set literals; sum of products expressions; window literals; Circuits; Costs; Decoding; Design optimization; Hardware; Input variables; Logic design; Minimization; Programmable logic arrays; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 1995. Proceedings., 25th International Symposium on
ISSN
0195-623X
Print_ISBN
0-8186-7118-1
Type
conf
DOI
10.1109/ISMVL.1995.513527
Filename
513527
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