A generic systolic processor for real time grayscale morphology

Mathematical morphology is a powerful and widespread tool for image analysis and coding, but for large analysis neighborhoods, it becomes rapidly time consuming on general purpose machines. Much work has been done to decrease the overall complexity by splitting heavy computation tasks into several more efficient ones. Even if significant speedup factors have been achieved using dedicated architectures, the major drawback is that the number of operations required is still dependent on the considered neighborhood size. This paper introduces a systolic network for real time grey level morphological processing since it is able to perform erosions, dilations, openings, and closings during a unique image pass whatever the neighborhood shape and size. It is based on a new structuring elements recursive decomposition by two pixels dilations and union sets. The resulting architecture is fully regular, built from elementary interconnected stages. By pipelining these stages timing performances are independent of the structuring element complexity. Efficient synthesis has been achieved into a FPGA enabling dual port ram implementation