Title :
Cellular nonlinear network implementation for nonlinear B-template
Author :
Paasio, Ari ; Halonen, Kari
Author_Institution :
Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo
Abstract :
A design for a nonlinear B-template is overviewed. The design is targeted for a 0.25 micron digital CMOS process. The transistor level schematics are given together with simulation results. Also the layout is reported
Keywords :
CMOS digital integrated circuits; SPICE; cellular neural nets; image segmentation; integrated circuit layout; neural chips; video signal processing; 0.25 micron; 0.25 micron digital CMOS process; cellular nonlinear network; nonlinear B-template; CMOS technology; Cellular networks; Cellular neural networks; Circuit simulation; Electronic circuits; Hardware; Laboratories; Output feedback; Silicon; Wire;
Conference_Titel :
Cellular Neural Networks and Their Applications, 2000. (CNNA 2000). Proceedings of the 2000 6th IEEE International Workshop on
Conference_Location :
Catania
Print_ISBN :
0-7803-6344-2
DOI :
10.1109/CNNA.2000.877368
